Appendix A. Operation-by-device matrix

This appendix is the full per-operation, per-family status reference behind chapter 4. Read down a family column to see what compiles and runs on that chip, and read the status marks and note for the gate and the route.

Each row is one intermediate-language operation, grouped by operation class, with its status on each Mac engine family from the M1 through the M5. Chapter 4 summarizes this table; the cells here are the reference.

The status marks are fixed:

• Native: the operation compiles and runs on that family on the direct engine path.
• Family-gated: no path on the listed family, native from the family named in the note.
• Bridge: reachable only through a decompose, software fallback, or compiler-internal route, never as a standalone code-generated operation.
• No path: rejected on every family from the M1 through the M5, computed off-engine.

The family columns are M1 (H13, A13), M2 (H14, A14), M3 (H15, A15), and M4 and M5 (H16 and H17s, A16 and A17). The A11 and A12 engines are below the floor that runs any of this vocabulary and are out of scope for the table.

The M1, M2, and M5 columns are measured on physical silicon. The M3 column and the M4 part of the merged M4 and M5 column are decompile-derived predictions from the per-chip tables, so a per-cell status there is a predicted capability rather than a measured one.

The table covers the 187 intermediate-language operations the compiler exposes. Of these, about 108 are native on the M1: the full elementwise, compare, activation, convolution, pooling, structural, and quantization vocabulary, plus the reduction, normalization, softmax, square-root family, fused attention, tile, and space-channel set. Nine need the M2 or later: the texture-engine operations (crop-resize, resample, affine, hardware gather) and the rank and sort bridge (top-k, sort, dynamic slice). Four need the M3 or later: native sin and cos, the hardware random generator, and the whole-tensor argument reductions on the intermediate-language route. Thirty-seven are rejected on every family and decompose on the host. About twenty-four are compiler-internal: mapped but with no observed standalone code generation, reachable only inside a wrapping construct.

Per-chip numeric limits

The status of an operation is one axis; the numeric envelope it runs in is the other. Table A.1 gives that envelope across the five capability tiers, measured from the live compiler by calling every per-architecture parameter constructor on a single M1, and a dash marks an unsupported value. The older column is the pre-A13 legacy targets the compiler still has parameter tables for, below the floor of the operation-status table above.

Table A.1. The per-chip numeric limits of the engine, measured from the live compiler across the five capability tiers.

The four generational dividing lines are visible in this table. The M1 adds the depth and three-dimensional axis and every reduction-class operation. The A14 adds the texture engine. The A15 raises the reduction-to-transpose threshold from 192 to 384 and adds native trigonometry. The A16 quadruples the maximum tensor and transpose dimensions from 16384 to 65536.

Convolution, matrix multiply, and pooling

Table A.2 lists the convolution, matrix-multiply, and pooling operations with their per-family status and the lowering note for each.

Table A.2. Convolution, matrix-multiply, and pooling operations by device family.

The ne_ and pe_ rows are private engine-lane and planar-engine unit selections of the same convolution, matrix-multiply, pooling, and elementwise atoms, not separate operations.

Normalization

Table A.3 gives the normalization operations, native on every family from the M1.

Table A.3. Normalization operations by device family.

Elementwise arithmetic

Table A.4 gives the elementwise arithmetic operations, where only mod takes no engine path.

Table A.4. Elementwise arithmetic operations by device family.

Comparison and logical

Table A.5 gives the comparison and logical operations, the bitwise-logical ones decomposing on the host.

Table A.5. Comparison and logical operations by device family.

Activations

Table A.6 gives the activation operations, native on every family and most lookup-table backed.

Table A.6. Activation operations by device family.

Reduction

Table A.7 gives the reduction operations, where reduce_argmin is gated and reduce_prod takes no path.

Table A.7. Reduction operations by device family.

The whole-tensor argument reductions global_argmax and global_argmin follow the same gate as reduce_argmin: native on the intermediate-language route from the M3, reachable through the bridge on the M1.

Data movement and structural

Table A.8 gives the data-movement and structural operations, the largest class, spanning reshape, slice, gather, scatter, and the space-channel set.

Table A.8. Data-movement and structural operations by device family.

Image, resize, and texture

Table A.9 gives the image, resize, and texture operations, gated to the texture engine from the A14 with software fallbacks on the M1.

Table A.9. Image, resize, and texture operations by device family.

Quantization and dtype

Table A.10 gives the quantization and dtype operations, with the per-family streaming gates carried in the note column.

Table A.10. Quantization and dtype operations by device family.

Attention, control flow, and state

Table A.11 gives the attention, control-flow, and state operations, where the state pair is native and the control-flow operations are compiler-internal.

Table A.11. Attention, control-flow, and state operations by device family.

Recurrent cells

Table A.12 gives the recurrent-cell operations, none of which take an engine path; each unrolls on the host.

Table A.12. Recurrent-cell operations by device family.

Trigonometric, special, and math

Table A.13 gives the trigonometric, special, and math operations, where sin and cos go native from the M3 and atan is the one M1-native primitive.

Table A.13. Trigonometric, special, and math operations by device family.

Detection and sampling

Table A.14 gives the detection and sampling operations, the rank and sort bridge gated to the M2 and the random and tensor-list operations off-engine.

Table A.14. Detection and sampling operations by device family.